Jakub Paś

Continued device scaling into the nanometer region has given rise to new effects that previously had negligible impact but now present greater challenges to designing successful mixed-signal silicon. Design efforts are further exacebated by unprecedented computational resource requirements for accurate design simulation and verification. This paper presents a GPGPU accelerated sparse linear solver for fast simulation of on-chip coupled problems using nVIDIA and ATI GPGPU accelerators on a multi-core computational cluster and evaluate parallelization strategies from a computational perspective.