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GPGPU Accelerated Sparse Linear Solver for Fast Simulation of On-Chip Coupled Problems

Continued device scaling into the nanometer region has given rise to new effects that previously had negligible impact but now present greater challenges to designing successful mixed-signal silicon. Design efforts are further exacebated by unprecedented computational resource requirements for accurate design simulation and verification. This paper presents a GPGPU accelerated sparse linear solver for fast simulation of on-chip coupled problems using nVIDIA and ATI GPGPU accelerators on a multi-core computational cluster and evaluate parallelization strategies from a computational perspective.
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International Supercomputing Conference, Dresden, Germany

ISC has evolved into a high-powered international conference and exhibition that gives its attendees a global perspective on the cutting edge of HPC. As always, our conference program tackles hot HPC topics; this year, for example, we will have a panel session on “Green Computing”, a topic that was almost unknown just two years ago. ISC’s focus on future trends and developments can also be seen in this year’s keynote presentation by Prof. Dr. Satoshi Matsuoka of the Tokyo Institute of Technology, Japan, who will discuss “Everybody Supercomputes in the Next Generation Cyber-Science Infrastructure”.
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